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| this document provides an overview of the mpc555 microcontroller, including a block diagram showing the major modular components and sections that list the major features. the mpc555 member of the freescale mpc500 risc microcontroller family. 1 introduction the mpc555 device offers the following features: ? powerpc? core with floating-point unit 26 kbytes fast ram and 6 kbytes tpu microcode ram 448 kbytes flash eeprom with 5-v programming 5-v i/o system serial system: queued serial multi-channel module (qsmcm), dual can 2.0b controller modules (toucan tm ) 50-channel timer system: dual time processor units (tpu3), modular i/o system (mios1) 32 analog inputs: dual queued analog-to-digital converters (qadc64) submicron hcmos (cdr1) technology 272-pin plastic ball grid array (pbga) packaging 40-mhz operation, -40 c to 125 c with dual supply (3.3 v, 5 v) (-55 c to 125 c for the suffix a device) 32-bit architecture (powerpc isa architecture compliant) core performance measured at 52.7-kbyte dhrystones (v2.1) @ 40 mhz fully static, low power operation integrated double-precision floating-point unit precise exception model table 1. mpc555 features device flash code compression mpc555 448 kbytes code compression not supported product brief mpc555pb/d rev. 3, 2/2003 mpc555 product brief f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. n c . . .
2 mpc555 product brief block diagram extensive system development support ? on-chip watchpoints and breakpoints ? program flow tracking ? bdm on-chip emulation development interface 1.1 block diagram figure 1 is a block diagram of the mpc555. figure 1. mpc555 block diagram 1.2 key features the mpc555 key features are explained in the following sections. 1.2.1 four-bank memory controller works with sram, eprom, flash eeprom, and other peripherals byte write enables 32-bit address decodes with bit masks usiu rcpu burst interface 256 kbytes flash 192 kbytes flash 16 kbytes sram 10 kbytes sram l2u e-bus uimb qadc qadc qsmcm toucan tpu3 dptram tpu3 toucan mios1 l-bus imb3 u-bus f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc555 product brief 3 key features 1.2.2 u-bus system interface unit (usiu) clock synthesizer power management reset controller mpc555 decrementer and time base real-time clock register periodic interrupt timer hardware bus monitor and software watchdog timer interrupt controller that supports up to eight external and eight internal interrupts ieee 1149.1 jtag test access port external bus interface ? 24 address pins, 32 data pins ? supports multiple master designs ? four-beat transfer bursts, two-clock minimum bus transactions ? supports 5v inputs, provides 3.3-v outputs 1.2.3 flexible memory protection unit four instruction regions and four data regions 4-kbyte to 16-mbyte region size support default attributes available in one global entry attribute support for speculative accesses 1.2.4 448-kbyte flash eeprom memory one 256-kbyte and one 192-kbyte module page read mode block (32-kbyte) erasable external 4.75-v to 5.25-v program and erase power supply 1.2.5 26-kbytes of static ram one 16-kbyte and one 10-kbyte module fast (one-clock) access keep-alive power soft defect detection (sdd) 1.2.6 general-purpose i/o support address (24) and data (32) pins can be used for general-purpose i/o in single-chip mode nine general-purpose i/o pins in mios1 unit many peripheral pins can be used for general-purpose i/o when not used for primary function 5-v tolerant inputs/outputs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 4 mpc555 product brief key features 1.2.7 two time processor units (tpu3) each tpu3 module provides these features: ? a dedicated micro-engine operates independently of the rcpu ? 16 independent programmable channels and pins ? each channel has an event register consisting of a 16-bit capture register, a 16-bit compare register and a 16-bit comparator ? nine pre-programmed timer functions are available ? any channel can perform any time function ? each timer function can be assigned to more than one channel ? two timer count registers with programmable prescalers ? each channel can be synchronized to one or both counters ? selectable channel priority levels ? 5-v tolerant inputs/outputs 6-kbyte dual port tpu ram (dptram) is shared by the two tpu3 modules for tpu microcode 1.2.8 18-channel modular i/o system (mios1) ten double action submodules (dasm) eight dedicated pwm sub-modules (pwmsm) two 16-bit modulus counter submodules (mcsm) two parallel port i/o submodules (piosm) 5-v tolerant inputs/outputs 1.2.9 two queued analog-to-digital converter modules (qadc64) each qadc provides: up to 16 analog input channels, using internal multiplexing up to 41 total input channels, using internal and external multiplexing 10-bit a/d converter with internal sample/hold typical conversion time of 10 s (100,000 samples per second) two conversion command queues of variable length automated queue modes initiated by: ? external edge trigger/level gate ? software command 64 result registers output data that is right- or left-justified, signed or unsigned 5-v reference and range f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc555 product brief 5 key features 1.2.10 two can 2.0b controller modules (toucan) each toucan provides these features: full implementation of can protocol specification, version 2.0a and 2.0b each module has 16 receive/transmit message buffers of 0 to 8 bytes data length global mask register for message buffers 0 to 13 independent mask registers for message buffers 14 and 15 programmable transmit-first scheme: lowest id or lowest buffer number 16-bit free-running timer for message time-stamping low power sleep mode with programmable wake-up on bus activity programmable i/o modes maskable interrupts independent of the transmission medium (external transceiver is assumed) open network architecture multimaster concept high immunity to emi short latency time for high-priority messages low power sleep mode with programmable wakeup on bus activity 1.2.11 queued serial multi-channel module (qsmcm) queued serial peripheral interface (qspi) ? provides full-duplex communication port for peripheral expansion or interprocessor communication ? up to 32 preprogrammed transfers, reducing overhead ? 160-byte queue buffer ? programmable transfer length: from 8 to 16 bits, inclusive ? synchronous interface with baud rate of up to system clock divided by 4 ? four programmable peripheral-select pins support up to 16 devices ? wrap-around mode allows continuous sampling for efficient interfacing to serial peripherals (e.g., ? serial a/d converters, i/o latches, etc.) two serial communications interfaces (sci). each sci offers these features: ? uart mode provides nrz format and half-or full-duplex interface ? 16 register receive buffer and 16 register transmit buffer (sci1 only) ? advanced error detection and optional parity generation and detection ? word length programmable as 8 or 9 bits ? separate transmitter and receiver enable bits and double buffering of data ? wakeup functions allow the cpu to run uninterrupted until either a true idle line is detected or a new address byte is received ? external source clock for baud generation ? multiplexing of transmit data pins with discrete outputs and receive data pins with discrete inputs, allowing realization of a low-speed serial protocol f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 6 mpc555 product brief key features 2 mpc555 address map the internal memory map is shown in figure 2. figure 2. mpc555 internal memory map 0x30 7 0x2f 0x30 0000 usiu & flash 16 kbytes 0x38 0000 (10 kbytes) 0x3f usiu control registers flash module a (64 b ytes) flash module b (64 b ytes) kbytes 0x2f c 000 0x2f 0x30 8000 0 x 3 7 ffff (4 80 kbytes) sr a m c ontr ol a ( 8 bytes) 0x3f 9800 (485.98 kbytes) 0x38 0010 res erved for usiu 2f c880 1 bfff ffff fff ffff 0x 0x2f c000 0x30 0000 0x30 7f80 0x30 7fff 0x30 7080 0x30 7480 0x30 7884 dptram (6 kbytes) qsmcm (4 kbytes) mios1 (4 kbytes) toucan_a (1 kbyte) toucan_b (1 kbyte) uimb registers (128 bytes) tpu3_a (1 kbyte) tpu3_b (1 kbyte) qadc_a (1 kbyte) qadc_b (1 kbyte) dptram control reserved (8180 bytes) reserved (2 kbytes) 0x30 2000 0x30 4000 0x30 5000 0x30 6000 reserved (1920 bytes) (12 bytes) imb3 address space 0x2f c800 0x2f c840 uimb interface & (32 kbytes) imb3 modules cmf flash a reserved for flash control reserved for imb3 reserved sram a 256 0x07 0000 0x00 0000 0x06 ffff 0x30 4400 0x30 4800 0x30 4c00 kbyte kbytes cmf flash b 192 sr a m c ontr ol b 0x38 0008 ( 8 b ytes) (16 kbytes) sram b 0x04 0000 0x3f c 000 (2.6 mbytes - 16 kbytes) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc555 product brief 7 key features 3 mpc555 pinout diagram figure 3 shows the pinout for the mpc555. figure 3. mpc555 pinout diagram mpc555 ball map 12345678 9 1 0 11 12 13 14 15 16 1 718 1 920 a vddh a_tpuc h1 a_ tpuch 4a_ tpu ch8 a _tpuch 12 a_t p u c h 1 5 vrl aan 0_pq b0 aa n48_ pqb4 a a n 52_p qa0 aan5 4_pq a 2ba n0_ p qb 0 ban2 _pqb2 b an3_ pqb3 ba n51_ p q b7 vddh md a11 m da12 md a 1 3 vddh b b_t2clk vddh a _ t puch6 a_tpuch10 a_tpuch 11 a_tpuch14 vrh aan3_pqb3 aan 49_pqb5 aan53_pqa1 aa n57_pqa5 ban1_pqb1 ban48_p qb4 ban52_pqa0 ban54_p qa2 e t rig2 mda14 m da15 vddh m da28 c b_ tpu c h 15 a_t 2clk a_ tpuch 3a_ tpu ch7 a _tp uch 9a_t p u c h 1 3 vdda aan 2_pq b2 aa n51_ pqb7 a a n 56_p qa4 aan5 9_pq a 7 ban49 _p qb5 b a n 5 3 _ pqa1 ba n56_p qa 4ba n57_ p q a5 e t r i g1 md a27 m da29 md a 3 0mda 31 d b_ t puch11 b_ t puch13 a_ t puch0 a_ t puch2 a_tpuch5 v ddi vssa aan1_pq b1 aan50_pqb6 aan55_pqa 3 aan58_pqa6 ban50_pqb6 b an55_pqa3 ban58_pqa6 ban 59_pqa7 vddi vdd l m pwm1 mpwm2 m pw m 3 e b _ tpu ch7 b_ t puch10 b_t puch 14 vd dl m pwm 0 mpwm 17 m pwm19 mpio6 f b_ t puch5 b_tpuch6 b_ t puch8 b_tpuch12 mpw m 16 m pw m 18 m pio7 mpio9 g b _ t p u ch2 b_tpuc h 3b_ tpu c h 4b_ tpu ch9 m pio5 mpio8 mpi o11 m pio12 h b_tpuch1 b_tpuch0 b_cnrx0 b_cntx0 mpio10 mpio15 mpio14 mpio13 j t ck_ dsck tdo_ d s do trst_b vdd sram vss vss vs s vss v f 2 _mpio2 vfls0 _mpio3 vf0 _mpio0 v f 1 _ m pio1 k tms tdi_d sdi s g p _ fr z vd dl vs s vss vss vss v d d l vfls1 _mpio4 a _cntx0 a _cn rx 0 l iw p 1 _ vf ls i wp 0 _vfls ir q3b _sgp irq4 b _sgp vss vss vs s vss p cs1 _qgp pc s0 _qgp miso _qgp4 m osi _qgp5 m irq0b _ s g p irq1b _sgp irq2b _ s gp sgp_ irqoutb vs s vss vss v ss pcs3 _qgp pcs2 _qgp eck sck _ qgp6 n web_ a t [0] brb_iwp2 bgb_lwp 1 bbb _iwp3 note : the pinout is a t op down vie w of t he package. rx d1_ qgpi txd1_ qgpo rxd2_ qgpi txd2_ qgpo p w e b_ a t[ 1 ] web_ at[ 2] web_ at[3 ] cs0b vpp epee v s s f v ddh r rd_ wr b cs 3 bc s2 bcs1b vdd l vddf xfc vd dsyn t oeb teab t si z 1 vddl vddi kapwr vsss yn extal u tsi z0 tab ts bbdip bvdd iaddr_ s gp31 add r _ sgp30 a ddr_ s g p 28 add r _ s gp29 vddl data_ s gp29 d a t a_ sgp27 d ata_ sgp25 da t a_ sg p 23 v ddl data_ s g p 20 r cfb _txp ext clk ec k _ buck xtal v burstb bib_stsb ad dr_ sgp11 addr_ sgp10 addr_ sgp9 addr_ sgp8 addr_ sg p22 addr_ sgp27 data_ sgp31 data_ sgp30 data_ sgp28 d ata_ sgp26 data_ sgp24 data_ sgp22 data_ sgp21 data_ sg p19 data_ sgp18 clkout poresetb sresetb w a dd r _ sgp12 v dd hadd r _ s gp14 a ddr_ sgp16 addr_ s g p 18 addr_ s gp20 addr_ sg p 23 addr_ s g p 26 d a t a_ sgp1 data_ s g p 3 d a t a_ s gp5 d ata_ sg p 7da t a_ s g p 9da t a_ sgp11 d a t a_ sgp13 data_ s g p 15 da t a_ sgp17 i r q5 b _sgp vdd h hre setb y vddh addr_ sgp13 addr _ sgp15 addr_ sgp17 addr_ sg p19 addr_ sgp21 addr_ sgp 24 addr_ sgp25 data_ sgp0 data_ sgp2 data_ sgp4 da ta_ sgp6 data_ sgp8 data_ sg p10 data_ sgp12 data_ sg p14 data_ sgp16 irq6b _mck2 irq7b _mck3 vddh vdd h =3 vo lt powe r (i/o ) v ddi = 3 v o l t po wer (in te rnal )v s s = gr ound vddh =5 vol t powe r =misc po wer y dees su bst ra te 9 /30 /97 a 21 n o vembe r 1997 v ersio n 10.2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 8 mpc555 product brief key features 4 supporting documentation list this list contains references to currently available and planned documentation. mpc555 user?s manual (mpc555um/ad) rcpu reference manual (rcpurm/ad) board strategies for ensuring optimum frequency synthesizer performance (an1282/d) using the mios on the mpc555 evaluation board (an1778/d) exception table relocation and multi-processor address mapping in the embedded mpc5xx family (an1821/d) non-volatile memory technology overview (an1837/d) designing expansion boards for the freescale evb555/etas es200 (an2001/d) mpc555 interrupts (an2109/d) emc guidelines for mpc500-based automotive powertrain systems (an2127/d) nexus standard specification (non- freescale document) nexus web site: http://www.nexus5001.org/ ieee 1149.1 specification (non- freescale document) 5 revision history table 2. revision history revision number substantive changes date of release 2 existing document. september 2001 2.1 added temperature range for suffix a device. 11 december 2002 3 updated template and formats. 11 february 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc555 product brief 9 key features this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . 10 mpc555 product brief key features this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc555 product brief 11 key features this page intentionally left blank f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mpc555pb/d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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